74LS125 PDF

ON Semiconductor 74LS Logic – Buffers, Drivers, Receivers, Transceivers parts available at DigiKey. description. These bus buffers feature three-state outputs that, when enabled, have the low impedance characteristics of a TTL output with additional. This device contains four independent gates each of which performs a non- inverting buffer function. The outputs have the 3-STATE feature. The 3-STATE.

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Major Brands 74LS Tri Unable to add item to List. Would you like to tell us about a lower price? This device contains four independent Gates each of which performs a non-inverting buffer function.

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This item can be shipped to select countries outside of the U. Don’t see what you’re looking for? Amazon Inspire Digital Educational Resources. We’ll e-mail you with an estimated delivery date as soon as we have more information. Be the first to review this item. Turn on 1-Click ordering for this browser. There’s a problem loading this menu right now. Ships from and sold by Amazon.

B00BY3M Item model number: See questions and answers. Product details Item Weight: Other Sellers on Amazon. Order now and we’ll deliver when available. Temporarily out of stock. Sorry, there was a problem. East Dane Designer Men’s Fashion. Image Unavailable Image not available for Color: Your account will only be charged when we ship the item. Share your thoughts with other customers. When enabled, the outputs exhibit the 47ls125 impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines 74lz125 external resistors.

When disabled, both the output transistors are turned off presenting a high-impedance state to the bus line. Alexa Actionable Analytics for the Web.

IC 74LS125

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74LS – Quad Bus Buffer

English Choose a language for shopping. Shopbop Designer Fashion Brands. Share Facebook Twitter Pinterest. Product features Dip 14 Supply voltage-nom vsup v: Thus the output will Act Neither as a significant load nor as a driver.

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Amazon Advertising Find, attract, and engage customers. Learn more about Amazon Prime. To minimize the possibility that two outputs will ATTEMPT to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs.

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